The present invention relates to time division multiplex arrangements.
Time division multiplex (TDM) techniques have been in widespread commercial use in a number of applications for quite some time. Notable among these are various telecommunications applications such as the internal architecture of a PBX and in the transmission of digital signals.
Central to typical prior art TDM arrangements is the notion of a "frame" divided into a predetermined number of the aforesaid time slots. The frame has a fixed, predetermined duration. Thus each time slot recurs at a fixed frequency, or rate, referred to herein as the "frame rate". For example, then, if the frame has a duration of 125 .mu.sec, each time slot recurs at a rate of 1/(125.times.10.sup.-6) sec=8 KHz. Each device communicating on the bus is assigned to one or more time slots and, when the time slot(s) occur, the device is enabled to place data on, and/or remove data from, the bus.
As long as the devices communicating on the TDM bus need to access the bus at a rate which is some multiple of the frame rate--so that each bus access rate is a multiple or submultiple of all the others--the assignment of time slots to particular devices and the actual communication of data over the bus are straightforward. For example, a device that needs to access the bus at a rate of 8 KHz is assigned a particular one time slot on the bus. A device that needs to access the bus at a rate of, say, 16 KHz would be assigned to a particular two time slots, and so forth. Indeed, devices that need to access the bus at some submultiple of the frame rate, such as 2 KHz, can also be accommodated by assigning one time slot to that device and allowing the device to use that time slot as needed, e.g., once every four frames in the 2 KHz case. It is even possible to allow such devices to share a time slot, thereby making maximum use of the bus capacity.
A problem arises, however, when the bus needs to accommodate devices whose bus access rates are such that there is at least one pair of the rates for which neither rate of the pair is a multiple of the other, e.g., 9.6 Kb/s and 64 Kb/s. One way of accommodating this situation is to have one or more of the devices operating in an asynchronous mode in which the device accumulates its data until some prespecified amount of data has been saved up. The accumulated data is then applied to the bus during the next occurrence of a time slot assigned to the device. For example, a device which needs to place 9.6 Kb/s data on an 8 KHz bus may be assigned a single time slot and required to accumulate its data in blocks of 8 bits, each of which blocks is then placed on the bus at the next occurrence of the assigned time slot.
Other approaches to this problem are also known. Common to all of them, however, is the fact that the data is communicated asynchronously. This, then, requires the recipient of the data to regenerate a clock signal for the data using, for example, phase-locked loops or other circuit schemes. Disadvantageously, such circuitry is relatively expensive. The known schemes, moreover, are wasteful of the capacity of the communication medium because, depending on the scheme employed, the assigned time slot will carry either (a) redundant information or (b) no information during many, if not a majority, of the frames.